Low Bit Rate Design and Implementation of BPSK Demodulation on FPGA

This paper présents extended Works on BPSK Modulation at Low Bit Rate and also presents Simulation results and FPGA implementation of BPSK demodulation at Low Bit Rate 1200 bits/second on Altera Stratix III Development Board. Here Binary Sequence ,Carrier Frequency and sampling frequency are user controllable in BPSK modulation that was designed already. So this paper present Design of BPSK Demodulation which demodulate pattern comes at output of BPSK modulation at 1200 bits/second. BPSK demodulation technique was analyzed using QuartusII 9.1 Complier. Design of BPSK Demodulation is completed using VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL). In BPSK Design one Mega Function ROM is used .BPSK Demodulation was done in Continuous mode. Here system Performance is measured in Noise by measuring BER of system and comparing BER performance to Ideal Theoretical performance.